This invention relates to a semiconductor memory device and, in particular, to a semiconductor memory device comprising a regular memory cell array which comprises a plurality of regular memory cells and a redundant memory cell array which comprises a plurality of redundant memory cells for being substituted for defective regular memory cells where defects occur therein.
As is well known in the art, the semiconductor memory device of the type described comprises not only a regular memory cell array but also a redundant memory cell array serving as a spare memory cell array in order to improve yield on manufacture.
The regular memory cell array comprises a plurality of regular memory cells which are arranged in the configuration of a matrix with M rows and N columns where M and N represent first and second positive integers each of which is not less than two. That is, the regular memory cell array comprises first through M-th rows each of which consists of N regular memory cells arranged along a column direction. In other words, the regular memory cell array comprises first through N-th columns each of which consists of M regular memory cells arranged along a row direction.
Similarly, the redundant memory cell array comprises a plurality of redundant memory cells which are arranged in the configuration of a matrix with P rows and N columns where P represents a third positive integer which is not less than two. That is, the redundant memory cell array comprises first through P-th rows each of which consists of N redundant memory cells arranged along a column direction. In other words, the redundant memory cell array comprises first through N-th columns each of which consists of P redundant memory cells arranged along a row direction. The redundant memory cell array may comprise a plurality of redundant memory cells which are arranged in the configuration of a matrix with M rows and P columns.
Before shipment of the semiconductor memory device, at least one of the first through the P-th rows of the redundant memory cell array is substituted for one of the first through the M-th rows of the regular memory cell array that is diagnosed as a defective part or row by a test and results in making the whole semiconductor memory device an acceptable product. The defective part or row of the regular memory cell array includes at least one defective regular memory cell. On the other hand, remaining rows other than the defective row are called acceptable rows each of which includes no defective regular memory cell.
Replacement of the defective row of the regular memory cell array with an acceptable row of the redundancy memory cell array is carried out by setting an address for the defective row of the regular memory cell array in a redundant decoder for the acceptable row of the redundancy memory cell by trimming fuse-elements in the redundant decoder. The redundant decoder puts the acceptable row of the redundancy memory cell array into an operating state when the redundant decoder is supplied with a predetermined address signal.
Description will proceed to a known replacement method of replacing the defective row of the regular memory cell array with the acceptable row of the redundant memory cell array. A test in the regular memory cell array for defects is carried out. When any defect is not detected in the regular memory cell array, it is made a judgment that the semiconductor memory device is an acceptable product. It will be assumed that any defect is detected in a regular memory cell in a row of the regular memory cell array as the defective row. In this event, trimming of fuse-elements in a redundant decoder for a particular row of the redundancy memory cell array is carried out to replace the defective row of the regular memory cell array with the particular row of the redundant memory cell array. After replacement of the defective row of the regular memory cell array with the particular row of the redundant memory cell array, a test in the particular row of the redundant memory cell array for defects is carried out. If any defect is detected in the particular row of the redundant memory cell array, it is made a judgment that the semiconductor memory device is a defective product. If no defect is detected in the particular row of the redundant memory cell array, it is made a judgment that the semiconductor memory device is the acceptable product.
Inasmuch as the known semiconductor memory device does not return to the former state once the trimming of the fuse-elements is carried out, it is impossible to carry out a test of the particular row of the redundant memory cell array before replacement. Nevertheless, a defect hardly occurs in the particular row of the redundant memory cell array after replacement in a case where the rows of the redundant memory cell array is few, namely, the third positive integer P is small. However, with more and more improved to make semiconductor memory devices have a larger storage capacity in recent years, the rows of the redundancy memory cell arrays increase, namely, the third positive integer P is large. As a result, a case where the replaced row of the redundant memory cell array is defective occurs. Under the circumstances, the semiconductor memory device becomes a defective product although other acceptable rows of the redundant memory cell array remain. For example, when it is diagnosed that the replaced row of the redundant memory cell array is defective after replacement, it is judged that the whole semiconductor memory device is the defective product.
A method of resolving such a problem is disclosed in Japanese Unexamined Patent Publication of Tokkai No. Hei 7-226,100, namely, JP-A 7-226,100. In the semiconductor memory device according to JP-A 7-226,100, a redundant decoder generates a decode inhibit signal for inactivating a regular decoder for a regular memory cell array when a test mode signal is supplied to the redundant decoder. On the other hand, by previously corresponding an external address signal to an address of a redundant memory cell array as 1:1 and specifying an external address signal at the time of a test mode, the redundant decoder supplies the redundant memory cell array with a redundant decoded signal to activate the redundant memory cell array. Accordingly, access to a redundant memory cell is performed, thereby, test of the redundant memory cell can be preformed before operation of replacing a defective memory cell with the redundant memory cell.
In the manner which will later be described in conjunction with FIGS. 4 through 6, the conventional semiconductor memory device according to JP-A 7-226,100 is however disadvantageous in that it has a large scale in circuitry in a case where application is made about the semiconductor memory device comprising the redundant memory cell array including a lot of rows or a lot of redundant memory cells. This is because the conventional semiconductor memory device must comprise the redundant decoder provided with an address decoding circuit for selecting one of a lot of redundant decoding circuits.